Exploring the Landscape of Phase-Locked Loop Architectures: A Comprehensive Review

Abstract

This paper aims to explore diverse landscape of Phase Locked Loops (PLLs), offering a comprehensive categorization and in-depth analysis of their underlying working principles. Addressing the challenges of differentiation within this complex field, the review meticulously examines a curated selection of prominent research papers and articles encompassing a diverse range of PLL types. The taxonomy, meticulously constructed based on architectural and functional criteria, classifies various PLL categories precisely, elucidating the modifications implemented for optimal performance. To further enhance comprehension, a detailed block diagram architecture of a typical PLL system is presented alongside a comprehensive table showcasing operational parameters across different categories. The review presents illustrative graphs of various operational parameters, which include Power Consumption, Phase Noise, Output Frequency, Area, Figure of Merit(FOM), and lock time, enabling the visualization of trends over time. This work provides a significant contribution thereby assisting the budding researchers with insights and comparisons.