Efficient Design of Control Logic Block in Dual Port Memory

Abstract

A dual port memory in QCA is a study of data in different ports, but the data conflicts are very difficult to identify. Dual port memory is mainly focused on the data priority. It can be generated from the design of the control logic block. Priority bit are used, where both ports access the same memory location. Dual port memory functionality can be identified with a priority bit. When the port having the same memory location, only the port having the high priority is selected and other port are discarded. But when the read operation are requested to both the ports at same locations, having no conflicts and both the ports are requested to perform read operations. Data conflicts on the SRAM cell can be overcome by discarding the lower priority completely. Priorities are defined in terms of the area and delay. The idea behind this work is to minimize the area and delay in the dual port memory and proposed a multilayer Cross-Over design to provide an efficiency to the dual port memory and simulation result of design are shown in QCA Designer Tool-2.0.