Design of Area and Power Efficient Multiplier Unit using Wallace T ree Algorithm

Abstract

In any processing system, the core data path element may be a multiplier that particularly associated with DSP applications, which concludes overall processing unit performance. In such system, the multiplier unit improves the performance will boost up the potential. The Cadence EDA performs for high-speed multiplier evaluation consisting 64 x 64 bit in ASIC Digital flow (RTL-GDSII). Using carry select adder and carry save adder, the proposed multiplier intend with Wallace structure for enhancing the speed criteria. Wallace rebate absorbs more time for designing because it is more complex and aberrant in format for better width. Real Time signal processor requires high productive capacity and fewer reaction time. A classic scheme could be today in IOT utilizations. The proposed method concentrates on designing low power and area efficient in digital flow using the Wallace tree algorithm. The 180 nm CMOS technology for pursuance and outcome are related with other existing methods in delay, area and dynamic power dissipation.