A Low Power CMOS Phase Frequency Detector in High Frequency PLL System

Abstract

The design of low power consumption for the different application and electronic product has become one of the challenges in high performance of Very Large Scale Integration (VLSI) design today. Therefore, many techniques have been introduced to minimize the power consumption and one of the technique is by using Multi-threshold Complementary Oxide Semiconductor (MTCMOS) power gating technique. This paper aimed to design a High Speed Phase Frequency Detector (HSPFD) using MTCMOS power gating technique implemented in 130 nm CMOS technology by using Cadence Virtuoso Tool. This design achieved a power consumption of 0.116 μW and frequency of 1.26 GHz. The result shows that the power consumption of HSPFD with MTCMOS power gating technique achieved about 67.14% smaller than conventional HSPFD while the frequency improved about 26%. The total area of the proposed HSPFD is 1423 μm2 (61.1100 μm x 23.290 μm). It can be conclude that, this design has better performance compared to previous work and it is suitable for applications like wireless communication system that need low power blocks to have long life battery.