FPGA Implementation of Area Efficient CMOS Multiplier using Fast Kogge Stone Look Ahead Logarithmic Adder

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Abstract

Though Multipliers play a major role in all digital processing systems, still there is a research challenge related with area, delay, power, speed and accuracy parameters. Basically multipliers contains more number of adders (i.e.,) multiplication is done by repetitive additions. Highest care should be taken on adders. Partial Products (PP) part is middle process between multiplier, multiplicand and final addition. Next one about the methodology that Serial/parallel, Pipeline/parallel, Floating/decimal, Array, Binary/BCD, Fixed/Variable, Gate Level/Transistor Level. All the predecessors are having more controversy parameters. The forthcoming research concentrated on parallel, pipelining, decimal, binary and transistor level.

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Malathi*, L., Bharathi, Dr. A., & Jayanthi, Dr. A. N. (2019). FPGA Implementation of Area Efficient CMOS Multiplier using Fast Kogge Stone Look Ahead Logarithmic Adder. International Journal of Recent Technology and Engineering (IJRTE), 8(4), 8445–8449. https://doi.org/10.35940/ijrte.d9714.118419

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