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Power-analysis attack on an ASIC AES implementation

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Abstract

The AES (Advanced Encryption Standard) is a new block cipher standard published by the US government in November 2001. As a consequence, there is a growing interest in efficient implementations of the AES. For many applications, these implementations need to be resistant against side channel attacks, that is, it should not be too easy to extract secret information from physical measurements on the device. This chapter presents the first results on the feasibility of power analysis attack against an AES hardware implementation. Our attack is targeted against an ASIC implementation of the AES developed by the ETH Zurich. We show how to build a reliable measurement setup and how to improve the correlation coefficients, i.e., the signal to noise ratio for our measurements. Our approach is the first step to link power estimations from data generated by a behavioral HDL simulator to real power measurements. © 2005 Nova Science Publishers, Inc. All rights reserved.

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APA

Örs, S. B., Gürkaynak, F. K., Oswald, E., & Preneel, B. (2005). Power-analysis attack on an ASIC AES implementation. In Embedded Cryptographic Hardware: Design and Security (pp. 51–66). Nova Science Publishers, Inc.

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