Improving the Quality of the High-Level Synthesis Estimation Results through Multi-Level Predictive Models

Abstract

This work presents a machine learning-based approach to improve the quality of the area and delay estimates produced by commercial High-Level Synthesis (HLS) tools. Raising the level of VLSI design abstraction has multiple significant advantages, but one major disadvantage though is the that the area and delay estimates are show significant higher errors as compared to logic synthesis.To address this, on this work we first investigate systematically the error introduced by commercial HLS tools. We then investigate the use of different predictive models to reduce the error between the area and delay reported after HLS vs.after logic synthesis. Finally, we propose a multi-level predictive model approach that increases the accuracy of a single predictive model approach significantly avoiding also catastrophic prediction errors that we have observed. We show that this approach is important using the example automatic HLS design space exploration showing that designers cannot fully rely on the results reported by the HLS tool to drive an automated explorer.