Coefficient Combined and Shift and ADD Implementation (CSSI) Based Tunable Multiplierless Rotator Design

Abstract

Signal processing algorithms like Discrete Fourier Transform, Discrete Cosine Transform, and Fast Fourier Transform Transforms find various applications in the field of Image processing, Wireless communication, Robotics, and many others. It covers basically three operations viz. Multiply, Shift and Accumulate. Hence if the input data goes on rising as in cases where high resolution is required the amount of multiply operations also rises significantly. For example the number of complex multiply operations in case of Discrete Fourier Transform is N2, where N is the number of points. Latency becomes an important issue which needs to be addressed in today’s era as we, humans, thrive for the fastest systems with maximum resolution. To reduce latency we need to either emphasize on reduction in amount of data to be processed or change the processing structure which can affect the overall time to output. Multiplierless techniques for this purpose has been always a research area as it helps in reduction of the later part. Coordinate rotation of digital computer (CORDIC) based techniques are well known for the Multiplierless implementation of the sinusoids. However it carries certain drawbacks viz. large number of iterations and accuracy. This paper provides Coefficient combined & shift and add implementation (CCSSI) based approach for the design of Multiplierless rotators for various transforms for multiple constant rotators as well. The approach improves the range of coefficients with respect to number of adders (the range taken is from 4 to 10 adders) and number of point (the range taken is from 1 to 64 points) compared to the existing approaches and is shown in the results. It also presents a novel tunable Multiplierless architecture.