Performance Evaluation of Logic Gates Based on Carbon Nanotube Field Effect Transistor

Abstract

Carbon Nanotube Field Effect Transistors (CNFETs) are being widely studied as the possible alternatives to the conventional silicon-MOSFETs. In this paper we have successfully designed the CNFET-based digital logic gates and compared them with the existing CMOS technology based logic gates. The designs are modeled using 32-nm technology for both CNFET and CMOS technology, using Stanford University's MOSFET-like CNFET model [6] [7] and 32-nm BSIM PTM (Predictive Technology Model) respectively. For CNFET-based circuits, the compact SPICE model including non-idealities, which has been used for simulations, is the standard model that has been designed for unipolar MOSFET-like CNTFET devices, in which each transistor may have one or more Carbon Nanotubes (CNTs). HSPICE simulations have been performed on the logic gates designed using both these technologies and their output behaviors have been extensively studied at different supply voltages keeping the designs at room temperature. The performances are evaluated in terms of power, delay and PDP to show that it is possible to reduce the delay and the power consumption of the logic gates by replacing the CMOS transistors of the design with the emerging CNFETs.