Energy recovery and logical reversibility in adiabatic CMOS multiplier

Abstract

Overcoming the IC power challenge requires signal energy recovery, which can be achieved utilizing adiabatic charging principles and logically reversible computing in the circuit design. This paper demonstrates the energy-efficiency of a Bennett-clocked adiabatic CMOS multiplier via a simulation model. The design is analyzed on the logic gate level to determine an estimate for the number of irreversible bit erasures occurring in a combinatorial implementation, showing considerable potential for minimizing the logical information loss. © 2013 Springer-Verlag Berlin Heidelberg.