A Survey on the Performance Analysis of FinFET SRAM Cells for Different Technologies

Abstract

This paper presents a survey on the performance analysis of FinFET SRAM Cells for different technologies. Industry requires high performance low power devices and memories. CMOS devices scaled down to reduce the size. As CMOS devices are scaled down the variation in the design metrics like SNM, Leakage power and delay increases. FinFET is an emerging technology in the VLSI design to overcome the drawbacks of CMOS. FinFET has become the most promising alternatives to conventional CMOS. In this paper, comparison of conventional CMOS, Independent-Gate (IG) and Tied Gate (TG) FinFET SRAM standard cells performance analysis is done with respect to leakage power, Static Noise Margin (SNM) and delay.