High-resolution short time interval measurement system implemented in a single FPGA chip

Abstract

This study proposes a high-resolution short time interval measurement system based on the Vernier delay line (VDL) method. It should be noted that the programmable delay elements (PDEs) in the Xilinx field programmable gate arrays (FPGAs) provide a novel realization of delay lines. The delay lines can provide an accurate delay difference of 50 ps, which is process, voltage and temperature (PVT) invariant. An excellent consistency for the delay lines can be achieved by adjusting the timing and layout to minimize the measurement errors. The resolution achieved was 58 ps. Experimental results indicate a measurement standard deviation of 36 ps, a differential nonlinearity (DNL) of 36 ps and integral nonlinearity (INL) of 14 ps. The system features high accuracy, easy implementation and low cost. © 2011 The Author(s).