Assertion-Based Verification of I2C Module Using SystemVerilog

Abstract

In today’s semiconductor verification field, SystemVerilog Assertions (SVAs) are one of the most important methodologies for functional verification. A representative verification technique is Universal Verification Methodology (UVM)-based verification, which utilizes a SystemVerilog class library. On the other hand, Assertion-Based Verification (ABV) using SVA allows hardware designs to be verified without requiring knowledge of SystemVerilog’s Object-Oriented Programming (OOP) concepts or UVM. Its syntax is intuitive and concise, enabling rapid detection of RTL (Register Transfer Level) bugs during the design and verification phases. This methodology significantly enhances productivity by drastically reducing the time required for semiconductor development. This paper proposes an ABV verification environment using SVA that is reusable in other verification environments for verifying the main functions of the Inter-Integrated Circuit (I2C), one of the serial synchronous communication protocols. Finally, through the development of the RTL design and simulation of the core functionalities of I2C, the key characteristics of I2C were verified using ABV with SVA.