Millimeter wave SOI-CMOS power amplifier with enhanced AM-PM characteristic

Abstract

This paper proposes a novel inter-stage load-pull characterization method to enhance the linearity of millimeter wave integrated power amplifiers (PAs) by minimizing their amplitude-to-phase (AM-PM) distortion without worsening their AM-AM or efficiency performances. The proposed method identifies the optimal solution for the inter-stage matching network which enables the synthesis of a driver stage AM-PM characteristic that is complementary to that of the power stage; consequently, reducing the overall AM-PM distortion of the PA. The proposed technique is applied to design a proof-of-concept 28-31 GHz PA demonstrator using 45 nm silicon-on-insulator CMOS technology. The measurement results obtained under continuous wave excitation at 29 GHz demonstrate an excellent AM-PM characteristic, with phase distortions as low as 0.2° at the 1-dB compression power level of 13.9 dBm and less than 1° at an output power level of up to 16 dBm (very close to the saturation power of 16.6 dBm). This enhanced AM-PM linearity improves the linearizability of the PA. This was confirmed by testing the PA with a 64 quadrature amplitude modulated test signal with an instantaneous bandwidth of 800 MHz. Without applying any digital pre-distortion (DPD) technique, the PA delivers a power added efficiency (PAE) of 8.7% at an average output power (Pavg) of 9.4 dBm while maintaining an error vector magnitude (EVM) of -25 dB. However, after applying a very simple memoryless DPD function with only four coefficients, the PA can operate at a higher Pavg of 11.1 dBm with a much better PAE of 12.2% while still maintaining an acceptable EVM of -25.2 dB. Thanks to the proposed technique, the PAE of the proposed PA can be improved by 40% with a very simple application of a low cost and low complexity DPD technique.