Use of sensitivities and generalized substrate models in mixed-signal IC design

Abstract

A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced noise. Accurate and efficient evaluation of the circuit during design is possible by taking into account such non-idealities. Techniques are presented to derive and use a set of constraints on substrate noise and on the geometric instances of the layout. Verification is performed using substrate extraction in combination with parasitic estimation techniques. To show the suitability of the approach, a VCO for a PLL has been designed and implemented in a CMOS 1 μm technology. The circuit has been optimized both at the schematic and at the layout level for power and performance, while its sensitivity to layout parasitics and substrate noise has been minimized.