A low power 8-bit current-steering DAC using CMOS technology

ISSN: 22783075
28Citations
Citations of this article
3Readers
Mendeley users who have this article in their library.

Abstract

Design of 8-bit current-steering DAC is proposed in this paper. The800 MHz conversion rate has been obtained by a fully custom designed new architecture. With the operating voltage of 1V and 180nm CMOS technology this DAC is designed. The power dissipation is of 42.92uw which is very low. The DAC will thus create a “stair stepping” analog output until digital input is met or the voltage supply is reached. The measured integral non linearity (INL) is less than ±0.31LSB and the static differential non-linearity error (DNL) is ±0.418 LSB.

Cite

CITATION STYLE

APA

Ramakrishna, P., Nagarani, M., & Hari Kishore, K. (2019). A low power 8-bit current-steering DAC using CMOS technology. International Journal of Innovative Technology and Exploring Engineering, 8(6), 137–140.

Register to see more suggestions

Mendeley helps you to discover research relevant for your work.

Already have an account?

Save time finding and organizing research with Mendeley

Sign up for free