TSV-integrated surface electrode ion trap for scalable quantum information processing

Abstract

In this study, we report about the design, fabrication, and operation of a Cu-filled through-silicon via (TSV)-integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between an ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrode numbers and evolving complexity. The integration of TSVs reduces the form factor of the ion trap by more than 80%, minimizing parasitic capacitance from 32 ± 2 to 3 ± 0.2 pF. A low RF dissipation is achieved in spite of the absence of the ground screening layer. The entire fabrication process is on a 12-in. wafer and compatible with the established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (∼30 min) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.