Nowadays in VLSI number of transistors integrated on a single silicon chip is increasing day by day and the complexity of the design is increases tremendously. This makes very difficult for the designer and EDA tools. As number of instances increases the run time and memory for implementing the design increases. This will make more pressure on the designer because if product is not completed within the time to market company will lost so much of money. Floorplanning is the basic building step for any hierarchical physical design flow. Floorplanning is taking more amount of time in entire design hierarchical flow. If floorplanning is not good the entire design will take more time and it will increase a greater number of iterations to complete the design. In the top-level chip planning the quality of the floorplanning depends on the proper alignment of blocks and easy to meet the timing and congestion. To reduce memory size of CPU and run time, in this project we are using a method of Backbox model based top level hierarchical floorplanning based physical design. The main aim of this project is to reduce the number of instances which are not necessary in the top level chip floor planning which reduces peak memory for the design and also reducing CPU run time for getting proper prototype design in the top level ASIC design and estimate the congestion in the design at initial stage and modify floor planning to obtain quality of prototype model in the floorplanning. This project is designed on cadence encounter tool.
Kallam, R. R., & Gundala, S. (2019). Blackbox model based VLSI hierarchical floorplanning. International Journal of Engineering and Advanced Technology, 8(6), 2604–2607. https://doi.org/10.35940/ijeat.F8754.088619
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