Abstract
Current caches are not adequate for vector operations. A new kind of support for vector operations, called prefetch unit, is designed to improve the performance of the scalar (SISD) processors. The prefetch unit can be used for any SISD architecture and also for many kinds of MIMD architectures. It may run in parallel and asynchronously with other parts of processor. It keeps of the history of memory reference, and initializes rarely any superfluous prefetches.
Cite
CITATION STYLE
Sklenar, I. (1993). Prefetch unit for vector operations on scalar computers. In Proceedings of the Ninth Annual International Symposium on Computer Architecture (p. 430). Publ by ACM. https://doi.org/10.1145/142880.142891
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