Modern Wireline Transceivers

Abstract

Over the past two decades, ever-increasing network bandwidth (BW) demands in data centers and high-performance computing systems have fueled exponential growth in per-lane serial link data rates. To keep up with this demand and enable faster communication over BW-limited electrical channels, wireline transceiver architectures and circuit topologies have rapidly evolved over this timeframe to support sophisticated modulation and equalization. This tutorial paper presents an overview of modern serial links. Application background is described, motivating the link energy efficiency and bit error rate (BER) requirements. Transmit and receive circuits and architectures are described for both short-reach and long-reach electrical interconnects. The former tends to rely on power-efficient analog/mixed-signal techniques to equalize relatively low-loss channels with reach up to a few cm, while the latter requires sophisticated digital signal processing (DSP) along with high-speed ADCs and DACs to compensate channels with loss greater than 30 dB at Nyquist. Optical links are reviewed in the context of intra-data center applications where they are increasingly used. Low-jitter, high-phase-accuracy clock generation and distribution techniques are examined. Finally, future directions for modulation, equalization, and error correction to support links exceeding 200 Gb/s are discussed.