Power Quality Event Detection and Classifier Architecture on FPGA for Smart M eters

Abstract

Smart meters have been developed to capture PQ events, detect the event, compress events and characterize events. The events are stored in local memory of smart meter as well are transmitted over communication channel. The smart meter hardware that performs complex signals processing activity such as event detection, classification and compression need to be implemented on reconfigurable platforms. FPGAs are used in smart meters as they support reconfigurability and also has inbuilt memory modules, processor modules and additional features for interfacing. High speed low power area efficient architectures for computation of Dual Tree Complex Wavelet Transform (DTCWT).