Design of 13T SRAM bitcell in 22nm technology using FinFET for space applications

Abstract

Majority of youngsters’ having connected online through internet either through computers or by smart phones. After the entry of Jio in the field of internet, the competition began and the cost of internet service became much cheaper andnoweveryone SRAM can be found in the cache memory which is a part of the RAM digital to analog converter. SRAM is used for high speed register and some of the small memory banks. The risk of these circuits and memory arrays which are capable to radiation effects than circuits powered at minimal supply voltages. when an high energy particle hits a sensitive node in a circuit soft errors like Single Event Upsets(SEUs)occurs. The attainment of radiation hardening of memory blocks is executing large bit cells or single Error Correcting Codes(ECCs). But ECC may require notable area, performance and leakage power penalties. The favorable device characteristic of FinFET avails them as a popular contender for the replacement of CMOS technologies. An optimal approach to reduce the leakage power of a 13T SRAM cell based on 22nm FinFET technology is proposed in this work. The circuit contains a dual-driven separated feedback mechanism to tolerate the upset with charge of deposits. Better immunity is supplied by this cell to soft errors when compared to 6T SRAM cell.