Delay and area optimization for FPRM circuits based on MSPSO algorithm

Abstract

To improve the area and delay of large-scale Fixed Polarity Reed-Muller (FPRM) logic circuit, an algorithm named multi strategy particle swarm optimization (MSPSO) is proposed. The whole population is divided into several child-groups with different study mechanism, and each group can corporate or compete with others. The Gaussian mutation is introduced to avoid the algorithm falling into local minima. Then, combined MSPSO with delay and area estimation model and polarity conversion, MSPSO is used to search the best polarity of FPRM circuit. Some MCNC Benchmark circuits are used to test the proposed algorithm, and the result shows that the MSPSO algorithm has good performance in FPRM circuit optimization. In addition, the average savings of area and delay is 33.17% and 13.28% in comparison with the other algorithm.