Design of efficient 16 bit crc with optimized power and area in vlsi circuits

Abstract

In Very-Large-Scale Integration (VLSI) application power and area are the vital factors for any digital circuits.This paper presented 16 bit Cyclic Redundancy Check (C RC) mapped in version v14.20-s013 1 of Cadence Encounter(R) RTL Compiler. The codes in numerous instances are visible to be advanced at block lengths of realistic hobby when they're used on low-noise BCCs.. By expeditiously mapping on cadence tool, Power is achieved small. The results of conversion are viewed mistreatment RTL synthesis cadence VIRTUOSO at 45nm technology. Supported digital signal process (DSP) architectures, the code for proposed low power is generated mistreatment 16 bit Cyclic Redundancy Check (CRC).