Use of CPU performance counters for accelerator selection in HLS-generated CPU-accelerator systems

Abstract

Modern HLS tools are capable of generating hybrid software-accelerator systems that target architectures containing both CPU and FPGA resources. However, given a particular application, it is often unclear how to best distribute the workload between the FPGA and the processor. This paper investigates the use of CPU performance counters for estimating the quality of hybrid CPU-accelerator systems generated by HLS tools. We find that although this method enables a rough order-of-magnitude performance estimation, it is rarely sufficient for the automatic selection of good accelerators. We show that accurate estimates can be achieved with a model that is aware of the HLS tool's capabilities - estimating accelerator performance to within 5% on average.