Analysis and design of subthreshold leakage power-aware ripple carry adder at circuit-level using 90nm technology

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Abstract

The design space of Wireless Sensor Network mainly focuses on power-aware circuits. As the eventtriggering nature of the circuit places itself in Standby mode for longer time, the leakage power shoots up and increases its power consumption. Out of many leakage components, subthreshold leakage power (Psub-leak) is the dominant one, which is reduced by the proposed technique called Short-Pulse Power Gated Approach (SPOGA). The adder is the basic digital subsystem in the signal processing blocks and Ripple Carry Adder (RCA) is analyzed in the context of Psub-leak at circuit-level of abstraction using Cadence GPDK090. The Psub-leak reduces significantly with the 35% to 40% leakage savings in comparison with conventional and Multi-Threshold CMOS (MTCMOS) based RCA.

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Amuthavalli, G., & Gunasundari, R. (2015). Analysis and design of subthreshold leakage power-aware ripple carry adder at circuit-level using 90nm technology. In Procedia Computer Science (Vol. 48, pp. 660–665). Elsevier B.V. https://doi.org/10.1016/j.procs.2015.04.149

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