Butterfly-fat-tree topology-based fault-tolerant network-on-chip design using particle swarm optimization

Abstract

As the number of Intellectual Property (IP) cores integrated on-chip is increasing, communication between them becomes challenge. To mitigate this issue, a packet-based switching technique known as Network-on-Chip (NoC) has been proposed. In the deep sub-micron technology, NoCs are more sensitive to fabrication variations and tolerance accumulation. Hence, there is a need to develop reliable and efficient Fault-tolerant NoC designs. This paper presents a novel fault-tolerant NoC design for Butterfly-Fat-Tree (BFT) topology with flexible spare core placement using a Particle Swarm Optimization (PSO) based metaheuristic technique. Experimentations have been performed on several benchmarks reported in the literature, (i) by varying the network size with fixed fault percentage in the network and (ii) by varying the percentage of faults while fixing the network size. The results show improvement in terms of communication cost in BFT networks.