A Hardware-Efficient Chaotic PRNG Exploring Posit Arithmetic for Secure Image Encryption

Abstract

Chaotic systems are attractive for digital and embedded applications due to their inherent unpredictability and sensitivity to initial conditions, making them suitable for applications such as image encryption. However, their implementation in digital hardware often suffers from dynamical degradation caused by limited numerical precision, leading to short periodic orbits and significantly reducing their effectiveness in security-related applications. Additionally, embedded systems impose strict constraints on hardware resources. To address these limitations, this work proposes a hardware-efficient Pseudo-Random Number Generator (PRNG) based on a Sugeno-approximated sine-map implementation. The design targets image-encryption applications and is optimized for Field-Programmable Gate Array (FPGA)-based embedded systems. We first approximate the sine map using a lightweight Sugeno fuzzy inference system, replacing costly trigonometric operations and enabling implementation with only one addition unit and one multiplication unit; second, we introduce a perturbation mechanism to mitigate dynamical degradation; third, the system performance is evaluated by comparing the use of posit numerical representation with the IEEE 754 floating-point standard; finally, we validate the design using the NIST SP 800-22 tests and demonstrate its applicability as a component in a secure image encryption scheme. The proposed PRNG combines statistical robustness with hardware efficiency, overcoming the typical trade-off faced by chaotic map implementations in digital systems. By balancing security strength and hardware efficiency, the proposed PRNG offers a promising solution for secure image encryption and demonstrates strong potential in emerging domains, such as lightweight security applications.