Line‐edge roughness from extreme ultraviolet lithography to fin‐field‐effect‐transistor: Computational study

Abstract

Although extreme ultraviolet lithography (EUVL) has potential to enable 5‐nm half‐pitch resolution in semiconductor manufacturing, it faces a number of persistent challenges. Line‐edge roughness (LER) is one of critical issues that significantly affect critical dimension (CD) and device performance because LER does not scale along with feature size. For LER creation and impacts, better understanding of EUVL process mechanism and LER impacts on fin‐field‐effect‐transistors (FinFETs) performance is important for the development of new resist materials and transistor structure. In this paper, for causes of LER, a modeling of EUVL processes with 5‐nm pattern performance was introduced using Monte Carlo method by describing the stochastic fluctuation of exposure due to photon‐shot noise and resist blur. LER impacts on FinFET performance were investigated using a compact device method. Electric potential and drain current with fin‐width roughness (FWR) based on LER and line‐width roughness (LWR) were fluctuated regularly and quantized as performance degradation of FinFETs.