Braun's multipliers: Spartan-3AN based design and implementation

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Abstract

Problem statement: Multiplication is an essential airthematic operation for common Digital Signal Processing (DSP) applications, such as filtering and Fast Fourier Transform (FFT). To achieve high execution speed, parallel array multipliers are widely used. Approach: The field Programmable Gate Arrays (FPGAs) is currently the dominant and viable technology that could be implemented and reconfigured at the same time. Results: The Sparatn-3An FPGA resources utilization for 4×4, 6×6, 8×8 and 12×12 bit Braun's multipliers are obtained and Analysis Of Variance (ANOVA) presents that the 12×12 multiplier has significant difference than other three multipliers. The mean delay time for four multipliers shows that as the size of multiplier increases the mean delay time also increases. Conclusion: In essence, parallel multipliers based on the FPGA technology can provide better solution for DSP processor, medical imaging and multimedia. © 2011 Science Publications.

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APA

Rais, M. H., & Al Mijalli, M. H. (2011). Braun’s multipliers: Spartan-3AN based design and implementation. Journal of Computer Science, 7(11), 1629–1632. https://doi.org/10.3844/jcssp.2011.1629.1632

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