Nanopore-application CMOS potentiostat design with input parasitic compensation

Abstract

A low-noise area-efficient potentiostat design for nanopore applications is presented. By adopting a cascode amplifier and a Wilson current mirror, the input resistance is drastically decreased, which enables one to obtain a desirable bandwidth to detect DNA translocation events in nanopore sensors. A novel compensation technique is also proposed to relieve a deleterious effect by the input parasitic capacitances. © The Institution of Engineering and Technology 2014.