Implementation of an LDPC decoder for IEEE 802.11n using VivadoTM High-Level Synthesis

Abstract

The increasing complexity of hardware designs calls for design methodolgies that use more abstract design entries and increased automation of the implementation process. Highlevel synthesis (HLS) has been a research topic for the past 20 years, and current tools, such as Xilinx VivadoTM HLS promise to bring HLS to widespread use. In this paper we use Xilinx VivadoTMHLS to design an LDPC decoder for 802.11n. Forward error correction decoders are typically implemented in hardware due to the high processing requirements and therefore an LDPC decoder is an appropriate example to demonstrate the power of high-level synthesis