Noise immune Pseudo-stacked-wide keeper domino technique for ultra deep submicron technology

Abstract

The demand of high performance with low leakage has extensively exploited domino logics for high speed computing and microprocessor systems. But this benefit gets compromised with scaling of technology leading to increase in sub-threshold leakage and reduced noise immunity. This paper presents a new performance oriented circuit technique for higher noise immunity with ultra-low leakage and better speed design. The proposed circuit technique employs pseudo buffer along with stacking effect to reduce leakage and power dissipation. The modified keeper transistor in the proposed circuit helps to reduce circuit delay and also improve noise sensitivity. The simulation has been carried out using Cadence spectre 90nm technology with results indicating 57% to 68% less leakage and 77% less power dissipation. The Energy-Delay-Product for the proposed circuit is the lowest in comparison to other existing techniques. The high values of Average Noise Threshold Energy, Unity Noise gain and Energy Normalized Average Noise Threshold Energy proves the improvement in Noise robustness over the previous techniques.