Integrated placement for mixed macro cell and standard cell designs

Abstract

A program that performs automatic placement of integrated circuit layouts is described. The macro block placement program (MBP) places widely ranging mixes of macro blocks and standard cells into slicing layouts. It uses a minimum net-cut criteria to partition standard cells into flexible virtual blocks before block placement. Blocks are then placed using a simulated annealing optimization. The block placement algorithm evaluates placements based on both routing area costs and net costs. An adaptive move selection algorithm maximizes the annealing performance. A simple annealing-based optimization of the standard cell partitions completes the process.