Power-efficient 32 bit adder-subtractor with integrated logic design and leakage mitigation techniques

Abstract

The role of arithmetic circuits in all the signal processing units is of paramount importance and in which Adder-Subtractor circuit is indispensable. However, the increased transistor density in effect of technology miniaturization resulted in power dissipation or leakage. Since battery technology innovations cannot provide a better solution, circuit-level power-aware design is the ultimate choice of the design community. When high level processing units are involved with larger bit size circuits, adequate power is consumed and moreover, power dissipation completely squanders the static power. Hence, the key point to achieve low power solution at the design level is to reduce the design complexity and undesired consumption of power; for which a novel Integrated Logic Design (ILD) style and a novel Leakage Mitigation and Retention (LMR) technique are proposed. The proposed ILD and LMR design approaches are implemented in the design of 32 bit Adder-Subtractor circuit using Cadence 90nm technology node. The simulation result of the proposed circuit is compared with its conventional circuit and it is observed that the static power is reduced to nanowatt range from microwatts range. Thus, it is proved that the proposed 32 bit Adder-Subtractor is of power-efficient with its best low power design approaches.