Arqueologia da violência: pesquisas de antropologia política

Abstract

This paper presents a 0.18μm CMOS system on a chip (SoC) that is a hardware platform for the front-end of DVD-Multi recorders (FESOC). It has one 32 bit RISC CPU and one 16 bit DSP as well as most of necessary components for DVD recorders, except for an analog front end (AFE) and some memories. The necessary building blocks are a partial response channel maximum likelihood detector (PRML), a servo signal processor (SERVO), write strategy controller (WSC), a data processor (DP), and an AT-attachment packet interface (ATAPI), and a micro computer unit (MCU). The MCU has a custom bus with the 32 bit ARM7TDMI central processing unit (CPU) for front end system control, and intellectual property (IP) interfaces to integrate legacy IP blocks into this FESOC. The DP has another custom bus with an error correction circuit (ECC), and 37Kbyte SRAM for correcting errors. The ATAPI has the other custom bus with SDRAM controller for buffering data. This three-layered bus architecture enable this FESOC to work well with the bus of 16 bit-wide at 67 MHz for the 8x DVD operation, and to be implemented in short developing time. The FESOC is fabricated in 0.18μm 1-poly 5-metal CMOS technology. It contains 8.4 million transistors in a 46 mm2 die and consumes 1.4 W with a channel clock of 209.28 MHz in 8x operation mode. © 2005 IEEE.