A CMOS morlet wavelet generator

Abstract

The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a low power consumption, improve standard deviation (σ) control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5μm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.