Asic implementation of 12-bit radix-8 booth multiplier

Abstract

Multipliers are playing a vital role in DSP and Neural Networks applications. Many methods have been introduced to work on multipliers that offer high speed, less power consumption and reduced area. Booth Algorithm demonstrates an efficient way of signed binary multiplication. In this paper, physical design of 12-bit radix-8 booth multiplier for signed multiplication is presented with an aim to improve the performance metrics such as power, area and delay. The performance of 12-bit radix-8 booth multiplier is compared with the 64-bit radix-16 booth multiplier.