Design and Analysis of an Ultra-Dense, Low-Leakage, and Fast FeFET-Based Random Access Memory Array

Abstract

High static power associated with static random access memory (SRAM) represents a bottleneck in increasing the amount of on-chip memory. Novel, emerging nonvolatile memories such as spin-transfer torque magnetic random access memory (STT-RAM), resistive random access memory (RRAM), and ferroelectric field effect transistor-based random access memory (FeFET-RAM) are alternatives for replacing hardware kernels such as SRAM-based last level caches (LLC) due to their fast access times and lower leakage. In this paper, we study an ultra-dense FeFET-RAM based on 1-FeFET memory cells, and address potential disturbance issues at the array level. Disturbances are studied experimentally and via simulation. Experimental measurements are well correlated with modeling results suggesting that we have a good understanding of how disturbance issues will manifest themselves. That said, previous WRITE schemes for 1-FeFET arrays may: 1) exacerbate disturbances and 2) significantly degrade figures of merit (FoM) such as WRITE power. To address these issues, we propose the use of columnwise body connections to simultaneously overcome disturbances and reduce leakage currents during WRITES. We present detailed studies on how 1-FeFET memory cells and arrays (with columnwise body bias) fare when compared to traditional SRAM approaches and other emerging technologies. Notably, we benchmark the 1-FeFET memory against 1T + 1FeFET and 2T + 1FeFET designs proposed in early works, as well as SRAM, STT-RAM, and RRAM. Our evaluation of a 64 × 64 FeFET-RAM array shows that the area, READ delay, and static power are reduced by ∼ 5.3×, ∼ 1.5×, and ∼ 74×, respectively, when compared to an SRAM equivalent. Also, the 1-FeFET memory cell design shows ∼ 50× improvements in terms of WRITE energy with respect to STT-RAM and RRAM counterparts.