Abstract
The ever increasing demand for concurrent execution results in a significant escalation in the communication need, which has compelled the System-on-Chip architects to shift the focus to a more communication-centric design. With the emerging communication requirement, balancing the network load has become the essential requirement that profoundly influences the performance of the Network-on-Chips (NoC). The current work proposes an NoC topology along with a load balancing mechanism. The floorplan of the design yields optimized length interconnects. High bisection width and the presence of sufficient path diversity improves network performance significantly. Extensive experimentation has been done with the existing prevalent cube and tree-based networks. Across all the above cases, a minimum of 42% average latency improvement is found whereas, in the throughput, it is of 7%. Efficient load balancing comes with a minimum benefit of 29% on average network power consumption.
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CITATION STYLE
Bose, A., & Ghosal, P. (2020). A cube-tree hybrid NoC topology with 3D mirroring technique for load balancing. In NanoCoCoA 2020 - Proceedings of the 1st ACM International Workshop on Nanoscale Computing, Communication, and Applications, Part of the 18th ACM Conference on Embedded Networked Sensor Systems, SenSys 2020 (pp. 26–32). Association for Computing Machinery, Inc. https://doi.org/10.1145/3416006.3431278
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