Novel architecture for binary multiplication

Abstract

Multipliers is the basic unit for all signal processing applications and other applications. In all technology advancement it plays a vital role, the targets are low power consumption, increase in speed, reduction in area etc. The computations that are done by a modern computers that includes microcomputers and microprocessor is astronomical. Even with the high speed computer chips the process of the data coming from the devices all over the world requires efficient algorithms and to achieve the compatibility we need to use the chip area effectively. The most often encountered computation in data processing or signal processing is the operation of multiplication. This architecture is to present a novice solution to reduce the total area of the multiplier by modifying the partial products addition multiplier. Generally, to compute the data with high speeds modern hardware uses the Wallace tree or dadda multiplication techniques. By reducing the number of partial products addition the number of gates can be reduced used to obtain the final result. In this proposed method we reduced the real-estate of the chip by using more number of full adder in the earlier stages of the partial products addition which is not present in the conventional multipliers.