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Design of a 5.2-GHz CMOS Power Amplifier Using TF-Based 2-Stage Dual-Radial Power Splitting/Combining Architecture

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Abstract

In this paper, a transformer (TF)-based two-stage dual-radial power splitting/combining architecture with advantages of in-phase RF power splitting/combining scheme, compact splitting/combining network, uniform dc distribution, and symmetric dc current supply/return path is developed. To verify the feasibility of the architecture, a 5.2-GHz high-gain fully integrated PA is designed and fabricated on standard 0.18-μm CMOS technology. The CMOS PA transmits 30.1-dBm saturation power (Psat) with 22.2% power added efficiency (PAE) at 5.2 GHz. The measured power gain is 30.8 dB and the output 1-dB compression point (OP1dB) is 24.1 dBm. The EVM has been measured with IEEE 802.11ac WLAN modulated signals. Using the 20-MHz bandwidth OFDM 64-QAM modulated signal, the PA meets the WLAN EVM specification of 5.6% up to 19.8-dBm linear output power. For a high data rate of 80-MHz bandwidth OFDM 256-QAM signal, the PA transmits linear output power of 17 dBm with 2.5% EVM. To the best of our knowledge, the CMOS PA achieves the highest output power, the highest power gain, and the highest OP1dB with decent PAE among other reported fully integrated CMOS PAs around 5 GHz to date.

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Tsai, J. H. (2019). Design of a 5.2-GHz CMOS Power Amplifier Using TF-Based 2-Stage Dual-Radial Power Splitting/Combining Architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(10), 3690–3699. https://doi.org/10.1109/TCSI.2019.2915616

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