Low power networks-on-chip

Citations of this article
Mendeley users who have this article in their library.

You may have access to this PDF.


Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings. © Springer Science+Business Media, LLC 2011 All rights reserved.




Silvano, C., Lajolo, M., & Palermo, G. (2011). Low power networks-on-chip. Low Power Networks-On-Chip (pp. 1–287). Springer. https://doi.org/10.1007/978-1-4419-6911-8

Register to see more suggestions

Mendeley helps you to discover research relevant for your work.

Already have an account?

Save time finding and organizing research with Mendeley

Sign up for free