Effects of gate stack structural and process defectivity on high- k dielectric dependence of nbti reliability in 32 nm technology node PMOSFETs

Abstract

We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E ′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high- k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2are increased but is reduced by 11% when the SiO2interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.