Design of Non-Volatile Phase Change Memory for FPGA Architectures

Abstract

Phase change memory circuit has been designed to function as Non-Volatile memory circuit using 45nm and 90nm technology. The other non-volatile memory circuits like Flash and MTJ-MRAM are realized in 45nm and 90nm CMOS Technology in which their output behavioral characteristics, power and delay parameters are obtained in order to compare with performance of MTJ-MRAM and Flash memory circuits. The design has been carried out using Cadence Virtuoso – Electronic Design Automation (EDA) Software tool in Analog Design Environment (ADE), the advanced design and simulation is performed in virtuoso platform. The schematic for PCM is designed and simulations are carried out in 45nm and 90nm technology using a test environment. Further the work has been extended to design memory circuit that gives non-volatility which can be implemented for FPGA architecture. Existing FPGA architectures which are non-volatile based, have limitations and demands for a better computing memory to be integrated within. The present work brings out a novel Phase Change Memory design with better performance than existing flash based and anti-fuse based types of FPGAs and also better than MTJ-MRAM attributes. The present work compares attributes like power dissipation and delay of PCM with other non volatile memories used for FPGA architecture. Further PCM techniques indicate significant power and delay reduction when compared to MTJ-MRAM and flash memory circuit.