Exploration of heterogeneous fpga architectures

Abstract

Heterogeneous FPGAs are commonly used in industry and academia due to their superior area, speed and power benefits as compared to their homogeneous counterparts. The layout of these heterogeneous FPGAs are optimized by placing hard-blocks in distinct columns. However, communication between hard-blocks that are placed in different columns require additional routing resources; thus overall FPGA area increases. This problem is further aggravated when the number of different types of hard-blocks, placed in distinct columns, increase in an FPGA. This work compares the effect of different floor-plannings on the area of island-style FPGA architectures. A tree-based architecture is also presented; unlike island-style architectures, the floor-planning of heterogeneous tree-based architectures does not affect its routing requirements. Different FPGA architectures are evaluated for three sets of benchmark circuits, which are categorized according to their inter-block communication trend. The island-style column-based floor-planning is found to be 36%, 23% and 10% larger than a near-ideal non-column-based floorplanning for three sets of benchmarks. Column-based floorplanning is also found to be 18%, 21% and 40% larger than the tree-based FPGA architecture for the same benchmarks.