Design of low power delay cell for wide tuning voltage controlled oscillator for frequency synthesis applications

Abstract

This paper reports delay cell for Voltage Controlled Oscillator. The new circuit is designed and simulated in UMC_18_CMOS, 180nm process with 1.8V supply using Cadence tool. Main focus of this design is to achieve low phase noise and less power consumption. Proposed design is 4 stages differential ring VCO. The simulation results are presented with frequency range 2.3 to 4.7 GHz and Power consumption is 7.704 mW at maximum oscillation frequency with phase noise of-91dBc/Hz at offset of 1MHz and-120 dBc/Hz at offset of 10MHz. These results are back annotated to the model and accurate model in verilog-A has been presented.