ADVANCING SYSTEM INTEGRATION: VERILOG-BASED HARDWARE IMPLEMENTATION OF AN ASIC INTERFACE FOR THREE AMBA PROCESSORS

Abstract

This paper presents the development of a multi-AMBA system processor interface employing multiple AMBA processors. The primary goal of this interface is to establish connections between various AMBA AHB interfaces and external memory units such as RAM and REGISTER, leveraging the high-performance capabilities of AMBA AHB. The research delves into the utilization of ASICs to integrate processors and functional blocks into a System-On-Chip (SoC) configuration, enabling the execution of intricate applications. Within the ASIC environment, the research explores how processors communicate with their designated targets through an interface that standardizes the communication protocol for all targets. It underscores the challenges posed by data throughput and inter-processor/RTL communication in contemporary processors and suggests the concurrent use of multiple AMBA processors for accessing their respective targets. Additionally, the paper introduces an arbitration system for managing multiprocessor access and investigates the optimization of bulk data access while prioritizing crucial ASIC design constraints, including speed, low power consumption, and efficient area utilization. The proposed system was rigorously validated through simulation using Verilog HDL, yielding positive and promising results.