High-efficiency switched-capacitor dc-dc converter with three decades of load current range using adaptively-biased pfm

Abstract

A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 2.0 V to 0.9 V with a peak efficiency of 80% is implemented in a 0.18 µm CMOS process. An ultra-low-power voltage-controlled oscillator that generates a wide range of switching frequencies is proposed to extend battery runtime. An efficiency >70% for load currents in the range of 12 µA to 17.8 mA is achieved by implementing a novel adaptively-biased pulse frequency modulation (ABPFM) technique in the controller. A symmetric charge-discharge topology with two-phase time interleaving is used as a power stage to reduce the output voltage ripple to <72 mV over the entire load current range.