A 3.1 to 5 GHz CMOS transceiver for DS-UWB systems

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Abstract

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm2 die using standard 0.18 μm CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

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APA

Park, B., Lee, K. A., Hong, S., & Choi, S. (2007). A 3.1 to 5 GHz CMOS transceiver for DS-UWB systems. ETRI Journal, 29(4), 421–429. https://doi.org/10.4218/etrij.07.0106.0321

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